| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 19 | Novel Implementation of BIST Technique for High Fault Coverage in UART Authors:BANALA SAI ARUN KUMAR, S.P.SURESH NAIK |
0108-0111 |
Download | |
| IJVDCS 20 | Low Power Wireless Sensor Network for Building Monitoring Authors:P. SRAVN KUMAR, D. SUBBA RAO, M. PUSHPALATHA |
0112-0117 |
Download | |
| IJVDCS 21 | Realization of Parallel Prefix Adders for Power and Speed Critical Applications Authors:G. L. A. SANTHI, G. DEEPIKA |
0118-0123 |
Download | |
| IJVDCS 22 | Implementation of High Performance Convolutional Encoder and Viterbi Decoder Authors:CHANDINI BATCHALA, MANDAVILLI SRI HARI |
0124-0128 |
Download | |
| IJVDCS 23 | High Speed Fused Add-Multiply Operator Design Based On SQRT-CSLA Adder Authors:FATIMA BEGUM, GAJULA NARASIMHA RAO |
0129-0140 |
Download | |
| IJVDCS 24 | Low Power Counter Design By Using DTCPSFF Authors:V. VASAVI, V. PRIYADARSHINI |
0141-0144 |
Download | |
| IJVDCS 25 | An Advanced Stego-Image Processing with Optimized Bandwidth Authors:B. V. K. SAI, P. RAVI SANKAR |
0145-0147 |
Download | |
| IJVDCS 26 | Developing of AES Algorithm on FPGA Authors:S. SHYAM KUMAR, M. K. KHAN |
0148-0150 |
Download | |
| IJVDCS 27 | An Efficient Design of High Performance Voltage controlled Oscillator (VCO) using 45nm VLSI Technology Authors:ROOP CHANDRA SHAH, M. ABDULLAH |
0151-0154 |
Download | |
| IJVDCS 28 | Low Power Digital Front End Architecture of ECG Data Acquisition System Authors:B. S. ASWATHY, P. FINOLINA ESTHER |
0155-0160 |
Download | |
